Title SoC Verification Engineer
Location Austin, Select...
Referral Code 98274
Calxeda is headquartered in Austin, Texas. Our company mission is to bring revolutionary computational efficiency to the data center built around the ultra-low-power ARM architecture. Furthermore, we are developing server platform technologies that scale efficiently to thousands of processor nodes with balanced, high-performance network and storage acceleration techniques, and advanced power management features.
If you like the idea of being a key contributor, and you like the idea of working for a company that wants to change the industry, then we'd like to hear from you!
- Work closely with the team, review specifications, develop attributes, tests & coverage plans, define methodology & test benches.
- Work closely with design & micro-architecture teams to understand the functional & performance goals of the design.
- Stay abreast with design specs, conduct test plan reviews, develop block/full chip tests & triage of failures.
- Implement verification environments and systems that utilize VIPs (verification IP) from 3rd party companies to model external functions and ensure Calxeda logic properly interacts with these VIPs
- Ensure overall functionality, pre tape-out, of the SoC in its targeted application
- Have strong communication skills combined with good team-oriented approaches to lead the verification efforts in a specific area of the design
- Support gate level functional verification, run regressions, manage bug tracking, analyze code & functional coverage...etc.
- Work independently & manage deliverables to align with the project goals plus support cross-functional engineering efforts.
- BSEE/MSEE with 5+ years of Verification Experience
- Advanced knowledge of SOC architecture/design & in-depth knowledge of verification flow.
- Experience with Verilog, System Verilog, PERL and C
- ARM-based SoC and IP experience, AXI experience helpful
- Familiarity with verification methodologies, environments, automation and coverage
- Knowledge of industry standard interfaces, good understanding of Verilog, Verilog simulator and debug.
- Clear understanding of constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy.
- RTL and logic design understanding and experience
- Should be a team player with excellent communication skills and the desire to take on diverse challenges.